The library supports the Intel Ivy Bridge client part (model 58)
uncore PMU. The support is currently limited to the Coherency Box,
so called C-Box for up to 4 physical cores.
Each physical core has an associated C-Box which it uses to
communicate with the L3 cache. The C-boxes all support the same set
of events. However, Core 0 C-box (snb_unc_cbo0) supports an
additional uncore clock ticks event: UNC_CLOCKTICKS.
The following modifiers are supported on Intel Ivy Bridge C-Box
i Invert the meaning of the event. The counter will now count
cycles in which the event is not occurring. This is a boolean
e Enable edge detection, i.e., count only when there is a state
transition from no occurrence of the event to at least one
occurrence. This modifier must be combined with a counter mask
modifier (m) with a value greater or equal to one. This is a
c Set the counter mask value. The mask acts as a threshold. The
counter will count the number of cycles in which the number of
occurrences of the event is greater or equal to the threshold.
This is an integer modifier with values in the range [0:255].
Both the UNC_CBO_CACHE_LOOKUP and UNC_CBO_XSNP_RESPONSE requires two
umasks to be valid. For UNC_CBO_CACHE_LOOKUP the first umask must be
one of the MESI state umasks, the second has to be one of the
filters. For UNC_CBO_XSNP_RESPONSE the first umask must be one of
the snoop types, the second has to be one of the filters.
This page is part of the perfmon2 (a performance monitoring library)
project. Information about the project can be found at
⟨http://perfmon2.sourceforge.net/⟩. If you have a bug report for this
manual page, send it to firstname.lastname@example.org. This
page was obtained from the project's upstream Git repository
⟨git://git.code.sf.net/p/perfmon2/libpfm4⟩ on 2017-03-13. If you dis‐
cover any rendering problems in this HTML version of the page, or you
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you have corrections or improvements to the information in this
COLOPHON (which is not part of the original manual page), send a mail
June, 2013 LIBPFM(3)